1. Field of Invention
The present invention relates to a memory device and a manufacturing method thereof. More particularly, the present invention relates to a dynamic random access memory and a manufacturing method thereof.
2. Description of Related Art
When the semiconductor industry enters the deep sub-micron process, the size and dimension of devices keep decreasing, and for the conventional dynamic random access memory (DRAM) structure, the space that can be used for capacitors is increasingly smaller. On the other hand, due to the huge size of computer application software, the memory capacity needs to become larger. For the trend that the dimension of the device is reduced and the memory capacity needs to be increased, the manufacturing method for the capacitor of the conventional DRAM must be modified to meet the trend.
DRAMs can be classified into two types according to their capacitor structures: one is the DRAMs having stack capacitors, and the other is the DRAMs having deep trench capacitors.
FIG. 1 is a schematic cross-sectional view of a conventional DRAM having a deep trench capacitor. Referring to FIG. 1, the DRAM includes a deep trench capacitor 10 and an active component 20.
The deep trench capacitor 10 is disposed in the deep trench 102. The deep trench capacitor 10 includes a bottom electrode 104, a capacitor dielectric layer 106, a conductive layer 108, a collar oxide layer 110, a conductive layer 112, and a silicon nitride layer 114. The bottom electrode 104 is disposed at the bottom of the deep trench 102 in the substrate 100. The conductive layer 108 is disposed in the deep trench 102. The capacitor dielectric layer 106 is disposed between the sidewalls of the deep trench 102 and the conductive layer 108. The conductive layer 112 is disposed in the deep trench 102, and above the conductive layer 108. The collar oxide layer 110 is disposed between the sidewalls of the deep trench 102 and the conductive layer 112. Further, an isolation structure 116 is disposed in parts of the collar oxide layer 110 and the conductive layer 112, and in the substrate 100. An oxide layer 118 is disposed in the deep trench 102, and above the deep trench capacitor 10. Further, a silicon nitride layer 114 is disposed between the collar oxide layer 110 and the oxide layer 118.
The active component 20 is disposed on the substrate 100. The active component 20 includes a gate structure 120 and source/drain regions 122. The gate structure 120 includes a gate dielectric layer 124, a gate 126 and a cap layer 128. The gate dielectric layer 124, the gate 126 and the cap layer 128 are sequentially disposed on the substrate 100. The source/drain regions 122 are disposed in the substrate 100 at both sides of the gate structure 120, and the source/drain region 122 at one side is connected with the silicon nitride layer 114.
When a read operation is performed on the DRAM, the current in the deep trench capacitor 10 flows to the source/drain region 122 through the silicon nitride layer 114, passes a channel region 130 under the gate structure 120, and then flows out through a contact plug (not shown). However, when the level of integration is increased and the device size is reduced, the channel region 130 under the gate structure 120 is also shortened, and a short channel effect is generated, thereby influencing the device performance. Moreover, the silicon nitride layer 114 is used as a buried strap window (BS window), resulting in a high resistance of the buried strap, which also influences the device performance. Further, when there is a positive voltage in the deep trench, the substrate outside of the BS window forms a channel, which causes the device to generate leakage current.